1. Field of the Invention
The present invention relates generally to simulation apparatus, and more specifically to a device simulation technique for determining the effective channel length of a field effect transistor.
2. Description of the Related Art
The effective channel length of a field effect transistor is an important parameter that characterizes the electrical performance of the transistor. Accurate measurement of the effective channel length is important for implementation of precision devices. Due to the presence of ambiguous factors associated with the boundaries between the gate electrode and the source and drain electrodes and due to product variabilities, the effective channel length of each transistor differs uniquely from the design value which is usually determined by the physical length of the gate. Measurement of the effective channel length by using a source-drain resistance R and its relation to a channel resistivity r and an external resistance R.sub.EXT is known. According to this method, the following relation holds for a linear region of a field effect transistor where the drain voltage is sufficiently low: EQU R=r.times.L.sub.EFF +R.sub.EXT ( 1)
L.sub.EFF is the effective channel length of a field effect transistor and is given by the relation EQU L.sub.EFF =L.sub.GATE -.DELTA.L (1a)
where L.sub.GATE represents the physical length of the gate, and .DELTA.L is a deviation of the effective channel length L.sub.EFF from the gate length L.sub.GATE and is assumed to be constant. The channel resistivity r varies with the source-gate voltage and substrate-source voltage of the device while the external resistance R.sub.EXT is assumed to be constant. Source-drain resistances of several field effect transistors having different gate lengths are measured by applying a constant source-gate voltage. Plotting the measured resistances R as a function of the gate lengths L.sub.GATE of these transistors causes them to adopt a line having a gradient corresponding to the channel resistivity r. By varying the source-gate voltage and making measurements of source-drain resistances R on these sample transistors, a plurality of lines of different gradients are produced. As shown in FIG. 1, these lines intersect at a point which is uniquely determined by a set of .DELTA.L and R.sub.EXT. Using the .DELTA.L value, the effective channel length is determined.
The above-mentioned measurement method is also employed in the current device simulation technique to permit performance evaluation and to achieve low-cost development of large scale integrated chips. However, due to the use of a plurality of different sample transistors the current simulation technique requires a large amount of data to be processed, resulting in a long processing time.